1. Field of the Invention
The invention relates generally to memory systems used in digital computing systems and more particularly relates to a memory system which is comprised of a plurality of intelligent memory elements each capable of rapid, direct communications with one another, without host system intervention or supervision.
2. Description of the Prior Art
Digital computers are well known which are comprised of a combination of one or more central processing units (CPU), memory and input/output devices. The CPU is the "intelligence" of the host computer and typically uses memory, both internal and external to the host system, as storage and/or scratch pad space for performing arithmetic and logic operations. The input/output devices typically provide man/machine interfaces and are means to communicate with external systems, such as other computers, external storage devices, etc.
Memory systems are well known which themselves are "intelligent", i.e., can perform data processing and control functions in parallel with the host CPU. To accomplish this known systems have one or more control units, usually in the form of microprocessors, each dedicated to servicing predetermined portions of memory where the dedicated units act independent of the host CPU, but subject to its control. Such systems are known as distributed control memory systems.
Communications between the host system and the processor units in a distributed control memory system typically involves using an address/read/write scheme in combination with a communications bus. Communications are slow since the independent processing resources compete for time on the bus and all communication, even when effectively between memory elements only, is, in known systems, routed via the host CPU.
Using the known schemes for communicating with distributed control memory, certain operations require tying up the host CPU and the system bus for considerable amounts of time, particularly when a search or sorting operation is in progress. These types of operations, heretofore software oriented, require extensive passing of control between the host system and the distributed control. Even more time is expended resolving the aforementioned contention problem when the hardware architecture of the overall system provides for only a single path communication bus between the host CPU and distributed control memory.
As a result of the aforementioned problems it would appear to be desirable to minimize or eliminate the time consuming software bottlenecks that work to slow computer systems by off-loading, from software to hardware, tedious and frequent tasks, such as those, associated with sorting and searching. Off-loading these tasks would reduce software errors and speed up many applications. Specifically, applications like the creation of constant ordered lists by an operating system would be aided. The creation of these lists is slow and accrues significant overhead on operating-system software. Also, improved speed and reliability in performing the ultra-fast sorting required by specialized applications, such as graphics and artificial intelligence, would be achieved.
It also appears desirable to permit direct communication between the control portions of memory elements in a memory element array, without host system intervention. In addition to facilitating performance of the aforementioned "software" tasks, the host CPU and memory element controllers would then truly operate independently and more efficiently. Particularly in the case where a single shared bus is involved, contention problems would be held to a minimum by taking advantage of the speed with which the memory elements could directly get on to and off of the bus, thereby enabling preselected tasks to be optimally performed by hardware directly.